A scheme of a conventional IC design is depicted in FIG. 1. Generally, a hardware description language (HDL) at a register transfer level (RTL), e.g. Verilog HDL, is used by circuit designers to describe an IC to be developed. The function of the HDL is then verified by an electronic-design-automation (EDA) tool program, e.g. a Verilog simulator, so as to generate an HDL code S0. Subsequently, the HDL code S0 is synthesized with a constraint that is designated by designers to specify the target timing, size, . . . etc. to output an optimized circuit C0, which is so-called as synthesis with optimization (Step 101). On the condition that the pre-layout simulation complies with the requirement, a physical design of the circuit C0 is performed, which includes placement, clock tree synthesis, timing optimization, and routing (Step 102). Finally, a post layout circuit L0 is obtained. The major difference between L0 and C0 is that L0 is with cells inserted during clock tree synthesis and/or timing optimization.
If there are design errors or specification change, designers normally modify logical functions of the design directly on the post layout circuit L0, which is known as Engineering Change Order (ECO) in order to skip the time-consuming physical design of Step 102. Designers incrementally apply the corresponding change to the physical design and then repeat the original synthesis, placement, and routing process again. By directly adding minor modifications to the post layout circuit L0, instead of modifying the HDL code S0, time and effort can be saved so as to speed up the commercialization of products.
However, the conventional ECO is implemented by a manual process. That is, after the modified HDL code Sn is simulated and verified, it is necessary to manually locate the elements to be modified (e.g. n2) in the post layout circuit L0 according to the contents (e.g. f2) of the HDL code Sn (Step 103). Then ECO logic 100 is added to make minor modification to the post layout circuit L0 (Step 104). The manual task is difficult and time-consuming. Furthermore, when making the change on the post layout circuit L0, a modified element could have been optimized away, hidden inside another element or entitled with a meaningless name by the logic optimization process of synthesis. As a result, the modified element is hard to be located in the post layout circuit. Even if the modified element is successfully located, designers still have to take advantage of Boolean Algebras and their experience in logic circuit designs to pattern proper logic circuit elements, which is another time-consuming manual task.
For solving the above problems, a logic cone data structure which can be constructed by doing Fan-In Trace 20 on a logic circuit is applied, as shown in FIG. 2. Referring to FIG. 2, a hierarchical module-based logic circuit consists of logic cones. The definition of a logic cone as follows:    1. a logic cone must be with an end element and N start elements, where N=1, 2, 3, . . . n;    2. the end element can be a primary output port or a sequential element or an input pin of black boxes; and    3. the start element can be a primary input port or a sequential element or an output pin of black boxes.
In FIG. 2, the logic circuit has primary inputs i1, i2, i3, i4, and primary output o1, o2, and a sequential element implemented with a flip-flop f1. For the sequential logic cone 21, the end element is the flip-flop f1 and the start elements are the primary inputs i1 and i2. For the output logic cone 22, the end element is the primary output port o2 and the start elements are the primary input ports i2, i3 and i4. On the other hand, for the output logic cone 23, the end element is the primary output port o1 but there is only one input element, i.e. the sequential element f1. Accordingly, the logic circuit includes three logic cones 21, 22 and 23 with f1, o1 and o2 as end elements.
Some approaches have been proposed in U.S. Pat. Nos. 6,581,199 and 6,484,292 for improving the manual ECO. For example, referring to FIG. 3, a new (modified) HDL code Sn is synthesized for generating a circuit (Cn) by way of synthesis with optimization (Step 302). The original circuit C0 is then processed into a post layout circuit L0 by way of physical design (Step 304). Then in Step 306, the post layout circuit L0 and the modified circuit Cn are built with respective logic cone data structure by way of a Fan-In Trace process. The names of the logic cones are then compared to assign the logic cones with the same end element as cone pairs, and then apply Equivalent Check (EC) to find the cone pairs which are functionally non-equivalent. Such non-equivalent cone pairs are where the ECO is to be applied and thus called ECO cone pairs. The process of finding the ECO cone pairs is called ECO cone pair extraction. Next in Step 307, for each ECO cone pair, transfer (or remap using technology mapping) the ECO logic of Cn into L0 to get the post layout ECO circuit Ln.
A problem of the prior art is that the amount of the ECO logic can be much more than that of manual ECO if the modified element is not an end element of a logic cone. When the modified element is not an end element of a logic cone but located inside the logic cone, the amount of the extracted ECO logic will be more than that is necessary, and thus more trouble for physical design change is rendered in terms of timing and routing.
Please refer to FIG. 4 which illustrates an example of the ECO of FIG. 3. In the example, only the logic expression f2 of the HDL code S0 is changed. However, as the corresponding modified portion is hidden into the logic cone 40 after the operation 401 of synthesis with optimization, the end element of the ECO cone pair resulting from the ECO cone-pair extraction 402 is the output f3 rather than the logic gate n1 or n2. Therefore, minimum ECO cone pair with least ECO logic cannot be found by such a method, and the amount of the ECO logic obtained in the operation 402 is more than that obtained in the manual ECO.
Obviously, the prior art cannot obtain the minimum ECO cone pair by comparing the optimized post layout circuit L0 and modified circuit Cn. Furthermore, the amount of ECO gates 400 in the post layout circuit Ln will be much more than expected.